Many tools allow electronic integrated circuit (IC) designs to be assembled, simulated, debugged, and translated into hardware. In particular, this can be done in an electronic design tool (EDT) known as a high-level modeling system (HLMS). An HLMS allows a user to construct and debug a design in a high level and abstract setting and then automatically translates the design into low level hardware. The high level design consists of blocks, ports, signals, and levels of hierarchy; there are translated into concrete blocks, ports, signals, and levels of hierarchy in a hardware description language such as VHDL or Verilog. The portion of the HLMS that does the translating is called a “compiler”, and the translation process is known as “compiling”.
To achieve a high level of abstraction, an HLMS typically hides low level aspects of a design that are nevertheless required for the design to function properly in hardware. For example, clock ports and signals may only be implicit in the high level design, but must be explicit in hardware. Similarly, gateways (i.e., blocks through which signals are imported into a design, and exported to the outside) can be positioned anywhere in a high level design, but in hardware become top level input and output ports.
It is desirable and useful to have mechanisms that simplify compilation. These mechanisms must allow aspects of the high level design that are at best implicit and at worst entirely missing to be translated into concrete hardware blocks, ports, and connections. The mechanisms must also allow hardware blocks, ports, and connections to be positioned far from the locations they occupied in the high level design.